Last year, Silicon Valley Startup SiFive released the first open source SoC (system on a chip), which was named Freeform Everywhere 310. Now, going one step ahead from the embedded systems, the company has released U54-MC Coreplex IP, which is the world’s first RISC-V based 64-bit quad-core CPU that supports fully featured operating systems like Linux. The U54-MC Core’s high-performance and flexible memory system make it ideal for applications such as AI, machine learning, networking, gateways, and smart IoT devices. Before telling you about the new U54-MC, let me introduce you to the basics of RISC-V CPUs. The traditional Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC) do justice to their names and focus on the difficulty level of instructions as well as optimizations.

On the other hand, the RISC-V architecture is a free and open source ISA for processors, which can be produced or implemented by anyone, for free. ISA stands for Instruction Set Architecture and tells what a CPU needs to do.

Coming back to the latest development, U45-MC Coreplex takes RISC-V commercially into Linux processing applications. It has four U54 CPUs and a single E51 CPU; each of them run at 1.5GHz. U54 cores support the RV64GC ISA, which is expected to become standard ISA for RISC-V Linux devices.

SiFive is offering customers 100 prototype SoCs for $100,000, according to EETimes. The customers don’t need to provide any fee on third-party IP until the chips are shipped. U54-MC Coreplex also comes with a rich SDK with demo software. Currently, Microsemi and Arduino are the two announced customers of SiFive.


U54-MC RISC-V Core IP Key Features

  • Fully compliant with the RISC-V ISA specification
    • 32KB L1 I-cache with ECC
    • 32KB L1 D-cache with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts per core
    • Sv39 Virtual Memory support with 38 Physical Address bits
  • 4x RV64GC U54 Application Cores:
    • 4KB L1 I-Cache with ECC
    • 8KB DTIM with ECC
    • 8 Region Physical Memory Protection
    • 48 Local Interrupts
  • 1x RV64IMAC E51 Monitor Core:
  • Fully Coherent TileLink Bus
  • Integrated 2MB L2 Cache with ECC
  • Real-time capabilities:
    • Both the L1 Instruction Cache and the L2 Cache can be configured into high-speed deterministic SRAMs
  • CLINT for multi-core timer and software interrupts
  • PLIC with support for up to 511 interrupts with 7 priority levels
  • Debug with instruction trace
  • U54 Performance:
    • 1.7 DMIPS/MHz
    • 2.75 CoreMark/MHz


In 2018 Q1, U54-MC will be available with a development board. Currently, it’s available in a limited “early access” phase. Find more information on SiFive’s website.